1. Field of the Invention
This invention relates generally to dynamic random access memory devices (DRAMs), and more particularly, to a dynamic random access memory device allowing data to be read and to be written in a byte-by-byte basis and having a multibit configuration.
2. Description of the Background Art
A memory board for storing data in a computer system generally comprises a number of semiconductor memory devices. A number of semiconductor memories such as dynamic random access memories and static random access memories are mounted on the memory board, and these are connected through a great deal of wiring. In order to reduce the wiring on the memory board and power consumption, generally, the number of semiconductor memories mounted on the board needs to be decreased. It is desirable, therefore, to maintain necessary storage capacity and decrease the number of semiconductor memories on the memory board. It should be pointed out that in simplifying the control of semiconductor memories, it is also desirable to decrease the number of semiconductor memories.
FIG. 9 is a block diagram of a memory system (or a memory board) used for a personal computer as one example. Referring to FIG. 9, this memory system comprises dynamic random access memories (hereinafter referred to as a "DRAM") 201 and 202 each having an 8-bit configuration. An address decoder 203 decodes an address signal on an address bus in response to a memory request signal applied from a CPU. A RAM request signal determined by this decoding is applied to a timing controller 206. A refresh timer 204 generates a refresh request signal, and supplies it to timing controller 206. Timing controller 206 operates also in response to a read command and a write command from the CPU. Timing controller 206 applies a control signal to a control signal driver 208 in response to an applied control signal. Control signal driver 208 generates various clock signals /RAS, /CAS0 and CAS1, /WE and /OE necessary to operate DRAMs 201 and 202. A refresh address counter 205 generates a refresh address signal in response to a signal /REFAE generated from timing controller 206. An address multiplexer 207 accepts this refresh address signal and an address signal on the address bus, and applies multiplexed address signals MA0 through MA9 to two DRAMs 201 and 202. Data buffers 209 and 210 are connected to the CPU through a 16-bit data bus 211. Data buffer 209 processes the lower byte of data bits D1 through D8 in data of 2 bytes (16 bits). Data buffer 210 processes the higher byte of data bits D9 through D16. Data buffers 209 and 210 are connected to DRAMs 201 and 202, respectively. Therefore, DRAM201 stores a lower byte of data D1 through D8, and DRAM 202 stores a higher byte of data D9 through D16.
Conventionally, DRAMs 201 and 202 used in the computer system shown in FIG. 9 process data on a byte-by-byte basis, because a DRAM having a 8-bit configuration is on the market. In recent years, a DRAM 200 having a 16-bit configuration has come onto the market, so that it is possible to use one DRAM 200 in place of two DRAMs 201 and 202. As a result, the number of DRAMs used in the computer system has reduced, and therefore reduction and simplification in the wiring and reduction of power consumption in a memory system or a memory board have been achieved.
As a DRAM having a 16-bit configuration, the following types have been conventionally known. The first type DRAM allows reading and writing in response to two column address strobe (hereinafter referred to as "CAS") signals and one write enable (hereinafter referred to as "WE") signal. This type of DRAM will be referred to as a 2 CAS/1WE type hereinafter. The second type of DRAM allows reading and writing in response to one CAS signal and two WE signals. This type will be referred to as a 1CAS/2WE type hereinafter. Since DRAM 200 shown in FIG. 9 is operated in response to two signals /CAS 0 and /CAS 1, and one signal /WE, it is a 2 CAS/1WE type. In addition, the third type of DRAM allows reading and writing in response to one CAS signal and one WE signal. This type of DRAM will be referred to as a 1CAS/1WE type hereinafter.
When a DRAM has a 16 bit configuration, a DRAM of a 1CAS/1WE type allows reading and writing of data on a 2-byte-by-2-byte basis, that is, on a 16-bit-by-16-bit basis. A DRAM of 1CAS/2WE type allows reading of data on a 2-byte-by-2-byte basis, that is on a 16-bit-by-16-bit basis, and writing of data on a higher-byte-by-higher-byte or a lower-byte-by-lower-byte basis (an 8-bit-by-8-bit basis). A DRAM of 2CAS/1WE type processes data on a higher-byte-by-higher-byte or lower-byte-by-lower-byte basis (that is, an 8-bit-by-8-bit basis) in reading and writing.
FIGS. 10 through 13 are timing charts in a typical operation cycle of a DRAM of the aforementioned type. FIG. 10 shows operation in a higher byte reading cycle of a DRAM of a 2CAS/1WE type. This DRAM is operated in response to a signal /LCAS for a higher byte and a signal LCAS and a signal /WE for a lower byte. A signal /RAS falls after a signal /UCAS rises, so that a row address signal RA for designating data in a higher byte is accepted. A column address signal CA is also accepted in response to the fall of a signal /UCAS. At that time, a signal /WE maintains a high level, so that a reading operation is performed. In response to the fall of a signal /OE, readout data bits DQ9 through DQ16 in a higher byte are output.
Referring to FIG. 11, a higher byte write cycle in a DRAM of a 2CAS/1WE type is shown. In this case, column address signal for designating a memory cell in which data bits DQ9 through DQ16 in a higher byte are to be stored is accepted and data DQ9 through DQ16 are written in the designated memory cell.
Referring to FIG. 12, a reading cycle in a DRAM of a 1CAS/2WE type is shown. This DRAM is operated in response to a signal /CAS, a signal /UWE for a higher byte and a signal /LWE for a lower byte.
Referring to FIG. 13, operation of a lower byte write cycle in a DRAM of 1CAS/2WE type is shown.
A DRAM of a 2CAS/1WE type is often used, for example, in a memory system such as a personal computer shown in FIG. 9. The reason is that generally data is frequently processed on a byte-by-byte basis in a computer system. Therefore, the DRAM of a 2CAS/1WE type allowing reading and writing of data on a byte-by-byte basis, that is, on a 8-bit-by 8-bit basis is used. On the other hand, reading data on a byte-by-byte basis is not normally necessary in the field of image processing. In the field of image processing, data needs to be written in a DRAM on a byte-by-byte basis, but in a reading operation, data is normally processed on a word-by-word basis (that is, 2 byte) or on a 2-word-by-2-word basis. In such a field, therefore, a DRAM of a 1CAS/2WE type is used.
FIG. 14 is a circuit diagram of an input buffer circuit for a DRAM of a 2CAS/1WE type. Referring to FIG. 14, externally supplied signals /UCAS, /LCAS and /WE are supplied to bounding pads 31 through 33 provided on a semiconductor chip through gold wires 41 through 43, respectively. An input buffer circuit 2 for a 2CAS/1WE type is connected to receive the signals applied to bounding pads 31 through 33, and therefore input buffer circuit 2 outputs internal signals /UCAS, /LCAS and/WE and supplies them to a clock generator not shown.
FIG. 15 is a circuit diagram of an input buffer circuit for a DRAM of a 1CAS/2WE type. Similar to the one shown in FIG. 14, an input buffer circuit 3 for a 1CAS/2WE type is connected to receive externally applied signals CAS, /UWE and /LWE. This input buffer circuit 3 outputs internal signals /CAS, /UWE and /LWE and applies them to a clock generator not shown.
Input buffer circuits 2 and 3 shown in FIGS. 14 and 15 are similar to each other, but it should be pointed out that these are peculiar to DRAMs of 2CAS/1WE type and a 1CAS/2WE type, respectively. In other words, input buffer circuit 2 shown in FIG. 14 cannot be used as an input buffer circuit for a DRAM of a 1CAS/2WE type. An input buffer circuit 3 shown in FIG. 15 cannot be used as an input buffer circuit for a DRAM of a 2CAS/1WE type. In a manufacturing factory, therefore, it is necessary to produce two kinds of DRAM in which almost all circuit configurations are the same but only input buffer circuits are different from each other. Similar mask patterns which are different only in circuit patterns for the input buffer circuits have been prepared, and two kinds of production line composed of almost the same manufacturing process have been necessary. This brings about a decline of efficiency such as design efficiency, production efficiency and test efficiency in a semiconductor manufacturing factory. In addition to that, it should be also pointed out that drastically changing demand can not be readily met because the use of DRAMs to be manufactured is determined in an early stage of manufacturing.